1. Field of the Invention
The present invention relates to ultra wide bandwidth spread-spectrum communications systems, and, more particularly, to generating mono-cycles using full rail swing logic circuits.
2. Description of the Related Art
Transmission of encoded data using wavelets is known in the art. However, a problem with circuit known in the art which generate such wavelets is power consumption. That is, such circuits dissipate large amounts of power and current, including standby current.
An aspect of the present invention is to transmit mono-cycles having a quiet value close to the middle of the voltage range between VDD and 0 volts, that is, close to mid-rail.
Another aspect of the present invention is to interject a negative mono-cycle followed by a positive mono-cycle, or vice versa.
Yet another aspect of the present invention is to encode information in sequences of mono-cycles.
A further aspect of the present invention is to shorten the peak-to-peak period of each mono-cycle to 100 picoseconds, which is determined based upon gate propagation times, a design parameter defined by the technology and design technique used.
Moreover, an aspect of the present invention is to provide a full rail swing, symmetric monocycle.
To achieve the above-mentioned aspects, a mono-cycle generating circuit of the present invention comprises a control circuit, a multiplexer, and a driver switch circuit. The control circuit generates sets of timing pulses. The multiplexer selects one of the sets of timing pulses. The driver switch circuit outputs a mono-cycle based upon the selected set of timing pulses. The driver switch circuit comprises complementary sets of switches, each complementary set of switches including complementary amplitude pull-up/pull-down functions such that the output mono-cycle is a full rail swing mono-cycle.
Moreover, the present invention is an apparatus comprising a control circuit, a multiplexer, and a driver switch circuit. The control circuit receives an input clock signal and an input inverse clock signal, and outputting based upon the input clock signal and the input inverse clock signal, a first set of timing signals and a second set of timing signals. The multiplexer receives the first set of timing signals and the second set of timing signals, and receiving an input logical value. The multiplexer selects and outputs as selected timing signals one of the first set of timing signals and the second set of timing signals based upon the input logical value. The driver switch circuit receives the selected timing signals. The driver switch circuit comprises a first p-MOS transistor coupled to a first n-MOS transistor, and a second p-MOS transistor coupled to a second n-MOS transistor through a voltage divider. The selected timing signals comprise a first subset of timing signals and a second subset of timing signals, the first subset coupled to and controlling the respective gates of the first and second n-MOS transistors, and the second subset coupled to and controlling the respective gates of the first and second p-MOS transistors such that each of the p-MOS and the n-MOS transistors makes a state transition simultaneously to output a mono-cycle.
In addition, the present invention is an apparatus comprising means for receiving an input clock signal and an input inverse clock signal, and outputting based upon the input clock signal and the input inverse clock signal, a first set of timing signals and a second set of timing signals, and for outputting a set of timing signals, and a driver switch circuit receiving the timing signals. The driver switch circuit comprises a first p-MOS transistor coupled to a first n-MOS transistor, and a second p-MOS transistor coupled to a second n-MOS transistor through a voltage divider. The selected timing signals comprise a first subset of timing signals and a second subset of timing signals. The first subset is coupled to and controls the respective gates of the first and second n-MOS transistors, and the second subset is coupled to and controls the respective gates of the first and second p-MOS transistors such that each of the p-MOS and the n-MOS transistors makes a state transition simultaneously to output a mono-cycle.
These together with other objects and advantages which will be subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals refer to like parts throughout.